The present invention relates to circuits which generate clock signals, and more specifically to a circuit and method for generating a clock signal.
Digital systems typically require one or more clock signals which synchronize activities performed by different functional parts within the systems. It is desirable in such systems that the clock signals have fifty percent duty cycles. The term "duty cycle" is well known to mean the ratio of pulse width to total cycle time. Thus, for a fifty percent duty cycle clock signal, the clock signal is high for half the cycle time.
Known methods of generating a clock signal having a fifty percent duty cycle involve generating a signal having a frequency equal to twice the desired frequency and dividing the signal by two to remove any duty cycle distortion.
These methods suffer from high cost. For example, a 100 MHz crystal is more expensive than a 50 MHz crystal. These systems also consume high amounts of power, produce high amounts of radio frequency (RF) radiation, and degrade system performance. Finally, they produce clock signals whose duty cycles are difficult to measure during production testing.
Therefore, it would be desirable to provide a circuit and method for generating a clock signal which do not suffer from the disadvantages above. It would also be desirable that the circuit and method produce a clock signal having a steady state duty cycle which is not limited to fifty percent.